1. Field of Invention
The present invention relates to Non-volatile memory structure. More particularly, the present invention relates to a non-volatile memory device with CMOS logic process.
2. Description of Related Art
Non-volatile memory has its wide applications in various field, such as the multimedia or particularly to the portable multi-media applications including digital camera and audio player, or the smart cellular phone. All of these apparatus need to store data or contents when power is off. Nonvolatile memory then has various applications.
In the various applications for integration nonvolatile memory, from fabrication and operation point of view, it is desired to adapted in the standard CMOS LOGIC process. Those applications include software updates, storing ID code, manufacture code, and look-up table. However, incompatibility process between conventional stack gate EPROM/FLASH memory and CMOS LOGIC process leads to increase process integration difficulty and cost overhead. A single-poly EPROM (erasable programmable read-only memory) cell is then proposed to prevent process incompatibility issue. As known in the current conventional technology, a memory cell has an NMOS transistor and PMOS transistor placed adjacently. The PMOS gate in N-well works as control gate and inversion layer is formed when positive voltage is applied to N-well/P+ Diffusion node. However the space-apart region of N-well capacitor and EPROM cell causes a large cell size in the conventional design.
FIG. 1A is a circuit, schematically illustrating the conventional circuit design for EPROM. In FIG. 1A, an NMOS transistor with the gate FG is forming on a p-type substrate. However, in order to have the capability to store the binary data, the PMOS transistor is formed in N-well to serve the capacitor function, wherein the gate oxide layer with the gate and the substrate form as a capacitor.
FIG. 1B is drawing, illustrating the equivalent circuit in operation for the conventional EPROM. In FIG. 1B, the MOS transistor is coupled with a capacitor at the gate electrode. The gate electrode is then coupled to the word lines W0, W1, . . . Two adjacent cells has the common source region coupled to the voltage source VS, and each of the drain region is coupled to the bit line, BL0, BL1, BL2.
In the foregoing conventional design, it at least has several disadvantages. For example, the cell size is very large. This is because of device isolation limitation between P+ Diffusion in N-well to N+ Diffusion in P-well. Also and, it is not suitable for embedded Flash/EEPROM applications because the over-erase issue may be caused.